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HD74LV273A
Octal D-type Flip-Flops with Clear
REJ03D0330-0300Z (Previous ADE-205-273A (Z)) Rev.3.00 Jun. 25, 2004
Description
The HD74LV273A has eight edges trigger D-type flip-flops with clear in a 20-pin package. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low sets all outputs to a low state. Low-voltage and high-speed operation is suitable for batterypowered products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
* VCC = 2.0 V to 5.5 V operation * All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) * All outputs VO (Max.) = 5.5 V (@VCC = 0 V) * Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) * Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25C) * Output current 6 mA (@VCC = 3.0 V to 3.6 V), 12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information
Part Name HD74LV273AFPEL HD74LV273ARPEL HD74LV273ATELL Package Type SOP-20 pin (JEITA) SOP-20 pin (JEDEC) TSSOP-20 pin Package Code FP-20DAV FP-20DBV TTP-20DAV Package Abbreviation FP RP T Taping Abbreviation (Quantity) EL (2,000 pcs/reel) EL (1,000 pcs/reel) ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs CLR L H H H CLK X D X H L X Output Q L H L Q0
Note: H: High level L: Low level X: Immaterial : Low to high transition : High to low transition Q0: Output level before the indicated steady state input conditions were established.
Rev.3.00 Jun. 25, 2004 page 1 of 9
HD74LV273A
Pin Arrangement
CLR 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10
20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK
(Top view)
Absolute Maximum Ratings
Item Supply voltage range Input voltage range*1 Output voltage range*1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at 3 Ta = 25C (in still air)* Storage temperature Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to 7.0 -20 50 25 50 835 757 -65 to 150 Unit V V V mA mA mA mA mW C Conditions
Output: H or L VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
SOP TSSOP
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150C.
Rev.3.00 Jun. 25, 2004 page 2 of 9
HD74LV273A
Recommended Operating Conditions
Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOH Min 2.0 0 0 -- -- -- -- -- -- -- -- 0 0 0 -40 Max 5.5 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 85 Unit V V V A mA Conditions
IOL
A mA
Input transition rise or fall rate
t /v
ns/V
H or L VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V
Operating free-air temperature
Ta
C
Note: Unused or floating inputs must be held high or low.
Logic Diagram
1D CLK
11 3
1D 1Q C1 R
2
1Q
CLR
1
To Seven Other Channels
Rev.3.00 Jun. 25, 2004 page 3 of 9
HD74LV273A
DC Electrical Characteristics
Ta = -40 to 85C Item Input voltage Symbol VIH VCC (V) 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 0 3.3 Min 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 -- -- -- -- VCC - 0.1 2.0 2.48 3.8 -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 Max -- -- -- -- 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 -- -- -- -- 0.1 0.4 0.44 0.55 1 20 5 -- Unit V Test Conditions
VIL
Output voltage
VOH
V
VOL
Input current Quiescent supply current Output leakage current Input capacitance
IIN ICC IOFF CIN
A A A pF
IOH = -50 A IOH = -2 mA IOH = -6 mA IOH = -12 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND VI = VCC or GND, IO = 0 VI or VO = 0 V to 5.5 V VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.3.00 Jun. 25, 2004 page 4 of 9
HD74LV273A
Switching Characteristics
VCC = 2.5 0.2 V Ta = 25C Item Maximum clock frequency Propagation delay time Symbol fmax tPHL tPLH/tPHL tPHL tPLH/tPHL tSU th tW Min 55 45 -- -- -- -- 8.5 4.0 0.5 6.5 7.0 Typ 95 75 10.3 10.4 13.1 12.9 -- -- -- -- -- Max -- -- 19.0 18.3 22.8 22.1 -- -- -- -- -- Ta = -40 to 85C Min 45 40 1.0 1.0 1.0 1.0 10.5 4.0 1.0 7.0 8.5 Max -- -- 21.0 20.5 25.5 25.0 -- -- -- -- -- Unit MHz ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns ns ns CLR Q CLK Q CLR Q CLK Q Data CLR inactive CLR L CLK H or L VCC = 3.3 0.3 V Ta = 25C Item Maximum clock frequency Propagation delay time Symbol fmax tPHL tPLH/tPHL tPHL tPLH/tPHL tSU th tW Min 75 50 -- -- -- -- 5.5 2.5 1.0 5.0 5.5 Typ 140 110 6.9 7.1 8.7 9.1 -- -- -- -- -- Max -- -- 13.6 13.6 17.1 17.1 -- -- -- -- -- Ta = -40 to 85C Min 65 45 1.0 1.0 1.0 1.0 6.5 2.5 1.0 6.0 6.5 Max -- -- 16.0 16.0 19.5 19.5 -- -- -- -- -- Unit MHz ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns ns ns CLR Q CLK Q CLR Q CLK Q Data CLR inactive CLR L CLK H or L VCC = 5.0 0.5 V Ta = 25C Item Maximum clock frequency Propagation delay time Symbol fmax tPHL tPLH/tPHL tPHL tPLH/tPHL tSU th tW Min 120 80 -- -- -- -- 4.5 2.0 1.0 5.0 5.0 Typ 205 160 4.7 4.8 6.0 6.2 -- -- -- -- -- Max -- -- 8.5 9.0 10.5 11.0 -- -- -- -- -- Ta = -40 to 85C Min 100 70 1.0 1.0 1.0 1.0 4.5 2.0 1.0 5.0 5.0 Max -- -- 10.0 10.5 12.0 12.5 -- -- -- -- -- Unit MHz ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns ns ns CLR Q CLK Q CLR Q CLK Q Data CLR inactive CLR L CLK H or L FROM (Input) TO (Output) FROM (Input) TO (Output) FROM (Input) TO (Output)
Setup time Hold time Pulse width
Setup time Hold time Pulse width
Setup time Hold time Pulse width
Rev.3.00 Jun. 25, 2004 page 5 of 9
HD74LV273A
Output-skew Characteristics
Ta = 25C Item Output skew Symbol tsk (O) VCC = (V) 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min -- -- -- Max 2.0 1.5 1.0 Ta = -40 to 85C Min -- -- -- Max 2.0 1.5 1.0 Unit ns
Note: Skew between any outputs of the same package switching in the same direction. This parameter is warranted but not production tested.
Operating Characteristics
CL = 50 pF Ta = 25C Item Power dissipation capacitance Symbol CPD VCC = (V) 3.3 5.0 Min -- -- Typ 15.9 17.1 Max -- -- Unit pF Test Conditions f = 10 MHz
Noise Characteristics
CL = 50 pF Ta = 25C Item Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage Low-level dynamic input voltage Symbol VOL (P) VOL (V) VOH (V) VIH (D) VIL (D) VCC = (V) 3.3 3.3 3.3 3.3 3.3 Min -- -- -- 2.31 -- Typ 0.4 -0.4 2.9 -- -- Max 0.8 -0.8 -- -- 0.99 Unit V V V V V Test Conditions
Test Circuit
Measurement point
CL*
Note: C L includes the probe and jig capacitance.
Rev.3.00 Jun. 25, 2004 page 6 of 9
HD74LV273A
tr tf 90 % 50 % V CC th 90 % 50 % V CC VCC 10 % 0V
* Waveform - 1
Timing input 10 % t su
VCC Data input 50 % V CC tw VCC Input 50 % V CC 50 % V CC 0V 50 % V CC 0V
tr
tf 90 % 50 % V CC t PLH 90 % 50 % V CC VCC 10 % t PHL 0V
* Waveform - 2
10 %
Input
VOH In phase output t PHL 50 % V CC 50 % V CC VOL t PLH VOH Out of phase output 50 % V CC 50 % V CC VOL Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 3 ns, tf 3 ns 2. The output is measured one at a time with one transition per measurement.
Rev.3.00 Jun. 25, 2004 page 7 of 9
HD74LV273A
Package Dimensions
As of January, 2002
12.6 13 Max
20
Unit: mm
11
1
10
5.5
0.80 Max
2.20 Max
*0.20 0.05
0.20 7.80 + 0.30 -
1.15
1.27
*0.40 0.06
0.10 0.10
0 - 8
0.70 0.20
0.15
0.12 M
*Pd plating
Package Code JEDEC JEITA Mass (reference value)
FP-20DAV -- Conforms 0.31 g
As of January, 2003
12.8 13.2 Max 20 11
Unit: mm
2.65 Max
1 0.935 Max
10
7.50
*0.25 0.05
0.25 10.40 + 0.40 -
1.45
0.20 0.10
0 - 8
0.57 0.70 + 0.30 -
1.27
*0.40 0.06
0.15 0.12 M
*Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) FP-20DBV Conforms -- 0.52 g
Rev.3.00 Jun. 25, 2004 page 8 of 9
HD74LV273A
As of January, 2002
Unit: mm
6.50 6.80 Max 20 11
1
10 0.65 1.0 6.40 0.20 0.65 Max
*0.20 0.05
0.13 M
4.40
*0.15 0.05
1.10 Max
0.10
0.07 +0.03 -0.04
0 - 8
0.50 0.10
*Pd plating
Package Code JEDEC JEITA Mass (reference value)
TTP-20DAV -- -- 0.07 g
Rev.3.00 Jun. 25, 2004 page 9 of 9
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
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